Certain flash Analog-to-Digital (A/D) converters are capable of converting an analog input directly into a digital output in a single clock cycle. Such devices are therefore advantageously used in applications requiring high speed A/D conversions. Unfortunately, the resolution of flash A/D converter circuits tends to be limited compared to pipelined, cyclic, or over-sampled A/D converter circuits, which typically provide more accurate A/D conversions.
Internally, flash A/D converters often employ a string of voltage or current references followed by appropriate gain elements (voltage or current amplifiers) to amplify the difference between an applied analog input voltage and each of multiple reference voltages. Outputs of the gain elements are typically coupled to a string of comparator circuits that produce a digital output representative of the applied analog input voltage. One drawback, therefore, of flash A/D devices is the complex circuitry that is often necessary to implement high speed designs.
One aspect of the present invention is directed towards providing more desirable A/D converter circuits and methods than taught in the prior art.
In an illustrative embodiment, an array of transistor circuits is fabricated so that each transistor circuit in an array of transistor circuits has a switching threshold determined by intrinsic switching thresholds of at least one sensing transistor in a corresponding transistor circuit. The sensing transistors in a set of transistor circuits of the array can be fabricated to have common physical dimensions even though corresponding intrinsic switching thresholds of the transistor circuits can vary. Consequently, an A/D converter device can be fabricated by coupling an encoder to the output of the array of transistor circuits having unique switching thresholds.
In another embodiment of the present invention, an array of transistor circuits can include sensing transistors that have intrinsic switching thresholds that change depending on an applied reference voltage. More specifically, a switching threshold of the sensing transistors can be changed by setting respective bias voltages associated with corresponding transistor circuits. The sensing transistors need not be of a common physical dimension.
A gradient bias voltage can be produced by applying one or multiple reference voltages at contact points on a substrate so that different well biasvoltages are produced along the length of the substrate. Accordingly, an input voltage can be applied to an array of transistor circuits having different switching thresholds to produce a digital output that varies depending on the input voltage. The digital output of the transistor circuits can be decoded to determine the value of an analog input.
As mentioned, a set of transistor circuits in an array can be fabricated to have common physical dimensions. In one application, all of the sensing transistors in the array of transistor circuits have common physical dimensions. For example, each sensing transistor in the array can be fabricated so they are substantially the same size with each other even though corresponding intrinsic thresholds of the circuits vary.
A transistor circuit can include a complementary pair of transistors to form a functional electronic device. For example, a transistor circuit can include a pair of transistors fabricated using CMOS (Complementary Metal Oxide Semiconductor) technology. More specifically, a p-type FET (Field Effect Transistor) and n-type FET can be fabricated into an inverter or buffer circuit whose intrinsic switching threshold depends on an applied well biasvoltage. Other suitable technology can be used in lieu of CMOS fabrication techniques according to the principles of the present invention. Also, the array of transistor circuits is not limited to an array of inverters or buffers.
An array of transistor circuits can be fabricated in a semiconductor substrate including n-well and p-well regions. More specifically, an n-FET device can be fabricated in a p-well substrate while a complementary p-FET device can be fabricated in an n-well substrate. As mentioned, the combination of n-FET and p-FET devices can produce an inverter circuit whose output depends on an applied input voltage and a corresponding applied well biasvoltage.
An array of transistor circuits can be fabricated along a length of complementary p-type and n-type substrates. To vary the switching threshold of the transistor circuits such as inverters, a first reference voltage can be applied to one contact point of a substrate while a second reference can be applied to another contact point on the substrate. Consequently, a gradient voltage can be produced along a length of a substrate and, thus, well biasvoltages applied to transistor circuits formed in the substrate can vary along its length.
When the well biasvoltages applied to the transistor circuits varies depending on a position of the transistor circuit along the substrate, the switching thresholds of transistor circuits also varies along a length of the substrate. Thus, for a range of potential input voltages, a digital output of the array can be unique. In other words, a change in the input voltage can cause certain transistor circuits to change a state of their output. Thus, a user can determine a value of an input voltage based on the output of the array of transistor circuits.
In another embodiment, a switching threshold of each transistor circuit in an array of transistor circuits can be substantially similar so that at least a set of the multiple transistor circuits have a common switching threshold. More specifically, unique bias voltages are not necessarily applied to each and every transistor circuit in an array of transistor circuits.
Outputs of a tapped delay line can be coupled to inputs of the transistor circuits having a common switching threshold to produce an A/D device. In a specific application, each output tap of the tapped delay line includes a resistor-capacitor pair that is coupled to a corresponding transistor circuit. An input voltage is applied to one end of the tapped delay line so that the input voltage is minimally delayed at a near end of the tapped delay line while the input voltage is maximally delayed at the end of the delay line. Depending on a time when outputs of the transistor circuit changes state, a value of an input voltage applied to the tapped delay line can be determined.
Initially, the capacitors in the tapped delay line can be shorted to ground. Thereafter, an input voltage can be applied to the input of the tapped delay line. Depending on the level of the input voltage, certain outputs of the transistor circuits will trip to an opposite state at a predetermined time following application of the input voltage. A latch can be used to store a state of the output of the transistor circuits.
An array of transistor circuits can be calibrated by applying a known input voltage from a voltage source such as a DAC (Digital-to Analog converter) to the array of transistor circuits and determining an output bit sequence produced by the array of transistor circuits. The bit sequence can include a transition region of bits that correlate to the value of a particular input voltage.
The previously discussed aspects of the present invention are advantageous over the prior art. Specifically, an A/D converter device manufactured according to the principles of the present invention can be fabricated from an array of transistor circuits having at least some common physical dimensions. For instance, a sensing transistor of each transistor can be fabricated using common widths and lengths in a CMOS implementation. This aspect of the present invention alleviates the need to painstakingly change device settings to produce multiple uniquely sized transistor circuits to vary inherent switching thresholds of the transistor circuits. Further, any variation across the array are readily overcome through calibration. Circuitry of the A/D converter device according to the principles of the present invention is therefore simpler to manufacture and is less prone to fabrication defects.
In many applications such as those based on CMOS technology, A/D converters can be fabricated using fewer transistor devices or complex circuitry than used in the prior art. For example, a string of inverter devices having unique switching threshold characteristics can be employed in an A/D converter device. An inverter circuit is a simple implementation of both gain and comparator elements. Gain is inherent in the switching action of an inverter while the input/output characteristics of an inverter resemble those of a comparator. Functionality provided by a string of comparators and complex resistor ladder networks as in the prior art can be replaced with a string of inverter devices or buffers without the need for device size variation across the array as in the prior art. Since each transistor circuit or part thereof, is approximately equal in physical dimensions, the transistor circuits need not be unnecessarily large so that they are slow or cause excess power consumption. A use of large inverters can cause considerable loading on the front end sample/hold circuit driving the input of an input of the ADC. Such devices typically provide poor speed (bandwidth).
Another aspect of the present invention is directed towards a system and method of storing bit sequences in memory. For example, analog-to-digital conversions are supported by generating a string of bits corresponding to an input voltage. A contiguous bit sequence in the string of bits corresponding to a transition zone is then identified in which at least two adjacent bits are set to different logic levels. Based on a location of the contiguous bit sequence in the string of bits, at least a portion of the contiguous bit sequence is stored in memory along with a corresponding voltage value.
In one application, the string of bits is generated by applying an input voltage to an array of inverter circuits having different thresholds. Thus, the string of bits can be a difference code.
The memory for storing bit information can be divided into multiple segments. A segment of the memory can be allocated for storing multiple unique contiguous sequences of bits for different input voltages to an analog-to-digital converter device. Thus, each segment in memory can correspond to a location of the transition zone within a sequence of bits. Hence, multiple unique contiguous bit sequences in a segment can correspond to a set of possible A/D input voltages. Consequently, an input voltage can be identified by knowing the location of a transition zone and thereafter matching the transition zone of bits in a corresponding segment to a stored voltage value for the unique sequence of bits in the transition zone.
Yet another aspect of the present invention is directed towards a system and method of supporting A/D conversions. For example, an input voltage can be applied to an array of comparator circuits having different thresholds to generate a string of bits. At least one comparator circuit in the array can be selected or effectively removed from the circuit so it can be calibrated while a balance of the array of comparator circuits in the array are used to generate a digital output corresponding to an input voltage. In one application, the array of comparator circuits is an array of inverter circuits having different thresholds producing a thermometer or difference code. Consequently, an A/D converter circuit can be calibrated while it is used to perform A/D conversions.